Tunnel Field Effect Transistor using Charge Trap and Method for fabricating the same
The present invention relates to a tunnel field effect transistor using a charge trap and a method for manufacturing the same, in which a three-layer dielectric film is formed on a gate sidewall insulating film, to form a current through a charge trap, thereby solving the problem of changes in a thr...
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Main Authors | , , , |
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Format | Patent |
Language | English Korean |
Published |
23.03.2023
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Subjects | |
Online Access | Get full text |
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Summary: | The present invention relates to a tunnel field effect transistor using a charge trap and a method for manufacturing the same, in which a three-layer dielectric film is formed on a gate sidewall insulating film, to form a current through a charge trap, thereby solving the problem of changes in a threshold voltage. The tunnel field effect transistor using a charge trap comprises: a substrate including a vertical first surface and a horizontal second surface which is in contact with the first surface; a source region which is formed in the substrate and constitutes an L-type tunnel field effect transistor; a drain region; and a gate, wherein the gate sidewall insulating film with an oxide-nitride-oxide (ONO) structure is formed between the source region and the gate, such that during device operation, an energy band is formed through electron trapping in a nitride region of an ONO layer of the gate sidewall insulating film.
본 발명은 게이트 측벽 절연막에 3층의 유전막을 형성하여, 차지 트랩(charge trap)을 통하여 전류를 형성하여 문턱전압 변화 문제를 해결할 수 있도록 한 차지트랩 기술을 이용하는 터널 전계효과 트랜지스터 및 이의 제조 방법에 관한 것으로, 수직 방향의 제 1 면과 제 1 면에 접하는 수평 방향의 제 2 면을 갖는 기판;기판에 형성되어 L형 터널 전계 효과 트랜지스터를 구성하는 소스 영역; 드레인 영역; 게이트;를 포함하고, 소스 영역과 게이트 사이에 ONO(oxide-nitride-oxide) 구조의 게이트 측벽 절연막이 형성되어 소자 동작시에 게이트 측벽 절연막의 ONO(oxide-nitride-oxide)층의 nitride 영역의 전자 트래핑(electron trapping)으로 에너지 밴드를 형성하는 것이다. |
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Bibliography: | Application Number: KR20210124242 |