전도성 질화물 막의 핵형성을 위한 방법

• Main Authors: RICHARDS GAVIN, BAUM THOMAS H, WANG HAN, HENDRIX BRYAN C
• Format: Patent
• Language: Korean
• Published: 20.02.2023
• Subjects: BASIC ELECTRIC ELEMENTS; CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DIFFUSION TREATMENT OF METALLIC MATERIAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; METALLURGY; SEMICONDUCTOR DEVICES; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION

특정한 규소-함유 할라이드, 규소-함유 아미드 및 특정한 금속 전구체를, 질소-함유 환원 기체와 함께 이용하여 특정한 금속 질화물 기판 표면의 핵형성을 위한 개선된 방법론이 제공된다. 전처리 단계를 이용하는 동안, 방법론은 크게 개선된 핵형성을 나타내는데, 여기서 이러한 금속 질화물 막이 침착된 마이크로전자 장치 기판은 약 10Å 내지 약 15Å의 두께 및 약 1% 미만의 공극 영역을 갖는다. 일단 이러한 핵형성이 달성되면, 통상적인 레이어-업온-레이어(layer-upon-layer) 침착이 쉽게 일어날 수 있다. Provided is improved methodology for the nucleation of certain metal nitride substrate surfaces utilizing certain silicon-containing halides, silicon-containing amides, and certain metal precursors, in conjunction with nitrogen-containing reducing gases. While utilizing a pretreatment step, the methodology shows greatly improved nucleation wherein a microelectronic device substrate having such a metal nitride film deposited thereon has a thickness of about 10 Å to about 15 Å and less than about 1% of void area. Once such nucleation has been achieved, traditional layer-upon-layer deposition can rapidly take place.