3D SELECTION GATE STRUCTURE AND FABRICATION METHOD FOR 3D MEMORY

A semiconductor memory device and manufacturing methods are described. The semiconductor memory device includes a memory array including at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, wherein the memory array has at least one strapping region and at least one...

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Bibliographic Details
Main Authors KANG SUNG KWAN, KANG CHANG SEOK, LEE GILL YONG, KITAJIMA TOMOHIKO
Format Patent
LanguageEnglish
Korean
Published 10.02.2023
Subjects
ELECTRICITY
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Summary:A semiconductor memory device and manufacturing methods are described. The semiconductor memory device includes a memory array including at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, wherein the memory array has at least one strapping region and at least one strapping contact, the strapping contact connecting the select-gate-for-drain (SGD) transistor to a strapping line. 반도체 메모리 디바이스 및 제조 방법들이 설명된다. 반도체 메모리 디바이스는 적어도 하나의 SGD(select-gate-for-drain) 트랜지스터 및 적어도 하나의 메모리 트랜지스터를 포함하는 메모리 어레이를 포함하며, 메모리 어레이는 적어도 하나의 스트래핑 구역 및 적어도 하나의 스트래핑 콘택을 갖고, 스트래핑 콘택은 SGD(select-gate-for-drain) 트랜지스터를 스트래핑 라인에 연결시킨다.
Bibliography:Application Number: KR20220095551