CORE OF NEURAL PROCESSING UNITS AND METHOD TO CONFIGURE THE SAME

A core of a neural processing device is configured to efficiently process convolution per depth by maximizing a spatial feature map locality using an adder tree. A data path of an activation and weight is reversed, and a 2-to-1 multiplexer is at every 2/9 multiplier along a row of multipliers. Durin...

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Bibliographic Details
Main Authors SHIN JONG HOON, SHAFIEE ARDESTANI ALI, HASSOUN JOSEPH H
Format Patent
LanguageEnglish
Korean
Published 29.12.2022
Subjects
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A core of a neural processing device is configured to efficiently process convolution per depth by maximizing a spatial feature map locality using an adder tree. A data path of an activation and weight is reversed, and a 2-to-1 multiplexer is at every 2/9 multiplier along a row of multipliers. During a convolution operation per depth, the core operates using the RSxHW data flow to maximize a locality of a feature map. For a normal convolution operation, the data path of the activation and weight can be configured for a normal convolution configuration, wherein at this time, the multiplexer may be in an idle state. 신경 처리 장치의 코어는 가산기 트리를 사용하여 공간적 특징 맵 지역성을 최대화하여 깊이별 컨볼루션을 효율적으로 처리하도록 구성된다. 활성화 및 가중치의 데이터 경로가 반전되고, 2 대 1 멀티플렉서는 승산기의 행을 따라 2/9 승산기마다 있다. 깊이별 컨볼루션 연산 중에 코어는 RSxHW 데이터 흐름을 사용하여 작동하여 특징 맵의 지역성을 최대화한다. 정상적인 컨볼루션 연산을 위해, 활성화 및 가중치의 데이터 경로는 일반 컨볼루션 구성에 대해 구성될 수 있고 이 때 멀티플렉서는 유휴 상태일 수 있다.
Bibliography:Application Number: KR20220068209