THRESHOLD VOLTAGE DETERMINATION FOR CALIBRATING VOLTAGE BINS OF A MEMORY DEVICE

A processing device of a memory sub-system is configured to: identify a plurality of blocks allocated to a first voltage bin of a plurality of voltage bins of a memory device; identify a subset of the plurality of blocks having a post-program time (TAP) within a predetermined threshold time period f...

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Bibliographic Details
Main Authors MUCHHERLA KISHORE KUMAR, FEELEY PETER, NOWELL SHANE, PARTHASARATHY SIVAGNANAM, RATNAM SAMPATH K, KAYNAK MUSTAFA N
Format Patent
LanguageEnglish
Korean
Published 25.10.2022
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A processing device of a memory sub-system is configured to: identify a plurality of blocks allocated to a first voltage bin of a plurality of voltage bins of a memory device; identify a subset of the plurality of blocks having a post-program time (TAP) within a predetermined threshold time period from a second TAP associated with a transition boundary between the first voltage bin and a subsequent voltage bin of the plurality of voltage bins; determine a threshold voltage offset associated with the subset of the blocks; and associate the threshold voltage offset with the subsequent voltage bin. 메모리 서브 시스템의 처리 장치는 메모리 장치의 복수의 전압 빈들의 제1 전압 빈에 할당된 복수의 블록들을 식별하고; 제1 전압 빈과 복수의 전압 빈들의 후속 전압 빈 사이의 전이 경계와 연관된 제2 TAP로부터 미리 결정된 임계 시간 기간 내에서 프로그램 후 시간(TAP)을 갖는 복수의 블록들의 서브셋을 식별하고; 블록들의 서브셋과 연관된 임계 전압 오프셋을 결정하고; 임계 전압 오프셋을 후속 전압 빈과 연관시키도록 구성된다.
Bibliography:Application Number: KR20220046795