SRAM SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A SRAM MEMORY CELL STRUCTURE

A device includes memory cells. A first memory cell among the memory cells includes a first write port laid out in a first doped region and a first read port laid out in a second doped region. The first read port is separated from the first write port by a second write port of a second memory cell a...

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Bibliographic Details
Main Authors NIEN YI HSIN, LIAO HUNG JEN, FUJIWARA HIDEHIRO
Format Patent
LanguageEnglish
Korean
Published 02.09.2022
Subjects
ELECTRICITY
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Summary:A device includes memory cells. A first memory cell among the memory cells includes a first write port laid out in a first doped region and a first read port laid out in a second doped region. The first read port is separated from the first write port by a second write port of a second memory cell among the memory cells. 장치는 메모리 셀들을 포함한다. 메모리 셀들 중 제1 메모리 셀은 제1 도핑 영역에 레이아웃된 제1 기입 포트 및 제2 도핑 영역에 레이아웃된 제1 판독 포트를 포함한다. 제1 판독 포트는 메모리 셀들 중 제2 메모리 셀의 제2 기입 포트에 의해 제1 기입 포트로부터 분리된다.
Bibliography:Application Number: KR20220024600