MEMS SIGNAL PROCESSING CIRCUIT FOR TRIPLE-MEMBRANE MEMS DEVICE
삼중막 MEMS 디바이스는 서로 이격되는 제1 막, 제2 막, 및 제3 막 - 제2 막은 제1 막과 제3 막 사이에 있음 -, 제1 막과 제3 막 사이의 밀봉된 저압 챔버, 밀봉된 저압 챔버에서의 제1 스테이터 및 제2 스테이터, 및 삼중막 MEMS 디바이스의 출력 신호들을 판독하도록 구성된 신호 프로세싱 회로를 포함한다. A triple-membrane MEMS device includes a first membrane, a second membrane and a third membrane spaced apart from one...
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| Main Authors | , , |
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| Format | Patent |
| Language | English Korean |
| Published |
28.06.2022
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| Subjects | |
| Online Access | Get full text |
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| Abstract | 삼중막 MEMS 디바이스는 서로 이격되는 제1 막, 제2 막, 및 제3 막 - 제2 막은 제1 막과 제3 막 사이에 있음 -, 제1 막과 제3 막 사이의 밀봉된 저압 챔버, 밀봉된 저압 챔버에서의 제1 스테이터 및 제2 스테이터, 및 삼중막 MEMS 디바이스의 출력 신호들을 판독하도록 구성된 신호 프로세싱 회로를 포함한다.
A triple-membrane MEMS device includes a first membrane, a second membrane and a third membrane spaced apart from one another, wherein the second membrane is between the first membrane and the third membrane, a sealed low pressure chamber between the first membrane and the third membrane, a first stator and a second stator in the sealed low pressure chamber, and a signal processing circuit configured to read-out output signals of the triple-membrane MEMS device. |
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| AbstractList | 삼중막 MEMS 디바이스는 서로 이격되는 제1 막, 제2 막, 및 제3 막 - 제2 막은 제1 막과 제3 막 사이에 있음 -, 제1 막과 제3 막 사이의 밀봉된 저압 챔버, 밀봉된 저압 챔버에서의 제1 스테이터 및 제2 스테이터, 및 삼중막 MEMS 디바이스의 출력 신호들을 판독하도록 구성된 신호 프로세싱 회로를 포함한다.
A triple-membrane MEMS device includes a first membrane, a second membrane and a third membrane spaced apart from one another, wherein the second membrane is between the first membrane and the third membrane, a sealed low pressure chamber between the first membrane and the third membrane, a first stator and a second stator in the sealed low pressure chamber, and a signal processing circuit configured to read-out output signals of the triple-membrane MEMS device. |
| Author | FUELDNER MARC KOLLIAS ATHANASIOS WIESBAUER ANDREAS |
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| DocumentTitleAlternate | 삼중막 MEMS 디바이스를 위한 신호 프로세싱 회로 |
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| Snippet | 삼중막 MEMS 디바이스는 서로 이격되는 제1 막, 제2 막, 및 제3 막 - 제2 막은 제1 막과 제3 막 사이에 있음 -, 제1 막과 제3 막 사이의 밀봉된 저압 챔버, 밀봉된 저압 챔버에서의 제1 스테이터 및 제2 스테이터, 및 삼중막 MEMS 디바이스의 출력 신호들을 판독하도록... |
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| Title | MEMS SIGNAL PROCESSING CIRCUIT FOR TRIPLE-MEMBRANE MEMS DEVICE |
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