3- METAL LAYERS FOR A THREE-PORT BIT CELL

• Main Authors: CHABA RITU, YEAP CHOH FEI, LIU PING, MOJUMDER NILADRI NARAYAN, SONG STANLEY SEUNGCHUL, WANG ZHONGZE
• Format: Patent
• Language: English; Korean
• Published: 08.06.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

장치는 비트 셀에 커플링되는 제 1 금속층을 포함한다. 장치는 또한 비트 셀에 커플링되는 기록 워드 라인을 포함하는 제 3 금속층을 포함한다. 장치는 추가로, 제 1 금속층과 제 3 금속층 사이의 제 2 금속층을 포함한다. 제 2 금속층은 비트 셀에 커플링되는 2개의 판독 워드 라인들을 포함한다. An apparatus includes first means for routing current coupled to a bit cell. The apparatus includes third means for routing current. The third means for routing current includes a write word line coupled to the bit cell. The apparatus includes second means for routing current. The second means for routing current is between the first means for routing current and the third means for routing current. The second means for routing current includes two read word lines coupled to the bit cell.