METHOD OF OPTIMIZING A PROCESS WINDOW

• Main Authors: VELLANKI VENUGOPAL, HUNSCHE STEFAN
• Format: Patent
• Language: English; Korean
• Published: 15.02.2022
• Subjects: APPARATUS SPECIALLY ADAPTED THEREFOR; BASIC ELECTRIC ELEMENTS; CALCULATING; CINEMATOGRAPHY; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; ELECTROGRAPHY; HOLOGRAPHY; MATERIALS THEREFOR; ORIGINALS THEREFOR; PHOTOGRAPHY; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES; PHYSICS; SEMICONDUCTOR DEVICES

본 명세서에서는, 기판 상으로 패턴의 처리를 수반하는 디바이스 제조 공정을 위한 컴퓨터-구현되는 결함 예측 방법이 개시되고, 상기 방법은: 패턴으로부터 프로세싱 윈도우 제한 패턴(PWLP)을 식별하는 단계; PWLP가 처리되는 처리 파라미터를 결정하는 단계; 처리 파라미터를 이용하여, 디바이스 제조 공정으로 PWLP로부터 생성되는 결함의 존재, 존재 확률, 특성, 또는 이의 조합을 결정 또는 예측하는 단계를 포함한다. A defect prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising: identifying a processing window limiting pattern (PWLP) from the pattern; determining a processing parameter under which the PWLP is processed; and determining or predicting, using the processing parameter, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the PWLP with the device manufacturing process.