display device

One embodiment of the present invention relates to a display device which comprises: a first silicon transistor including a first semiconductor layer having a silicon-based semiconductor and a first gate electrode overlapped with the first semiconductor layer; a first oxide transistor including a se...

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Bibliographic Details
Main Authors KIM KI HYUN, LEE SEUL GI, PARK YOUNG GIL, LEE SUN WOO, CHOI GEUN HYUK, HAN JAE BUM
Format Patent
LanguageEnglish
Korean
Published 15.12.2021
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Summary:One embodiment of the present invention relates to a display device which comprises: a first silicon transistor including a first semiconductor layer having a silicon-based semiconductor and a first gate electrode overlapped with the first semiconductor layer; a first oxide transistor including a second semiconductor layer separated from the first semiconductor layer and having an oxide-based semiconductor and a second gate electrode; an upper insulation layer disposed on the first semiconductor layer and the second semiconductor layer; and a first connection electrode disposed on the upper insulation layer to be connected to the first semiconductor layer through a first contact hole which passes through the upper insulation layer and is connected to the second semiconductor layer through a second contact hole which passes through the upper insulation layer. In addition, the second semiconductor layer includes a channel area, source areas disposed on both sides of the channel area, and a drain area, wherein a first distance between the channel area of the second semiconductor layer and the first contact hole is about 2㎛ or greater. Accordingly, a high-quality image can be produced. 본 발명의 일 실시예는, 실리콘계 반도체를 포함하는 제1 반도체층 및 상기 제1 반도체층과 중첩하는 제1 게이트전극을 포함하는 제1 실리콘 트랜지스터와, 제1 반도체층과 이격되며 산화물계 반도체를 포함하는 제2 반도체층 및 제2 게이트전극을 포함하는 제1 산화물 트랜지스터와, 제1 반도체층 및 제2 반도체층 상에 배치되는 상부 절연층, 및 상부 절연층 상에 배치되며 상부 절연층을 관통하는 제1 콘택홀을 통해 상기 제1 반도체층에 접속하고 상부 절연층을 관통하는 제2 콘택홀을 통해 상기 제2 반도체층에 접속하는 제1 연결전극을 포함하고, 제2 반도체층은 채널영역, 채널영역의 양측에 배치된 소스영역 및 드레인영역을 포함하되, 제2 반도체층의 상기 채널영역과 제1 콘택홀 사이의 제1 거리는 약 2㎛ 이거나 그보다 큰, 표시 장치를 개시한다.
Bibliography:Application Number: KR20200068599