SYSTEM ON CHIP DATA PROCESSING METHOD THEREOF AND NEURAL NETWORK DEVICE

According to the present disclosure, a system-on-chip includes: a first memory configured to store first data; a second memory; and a data processing circuit configured to divide the first data obtained from the first memory into a plurality of pieces of division data, assign a plurality of tags to...

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Bibliographic Details
Main Author LEE JONG HYUP
Format Patent
LanguageEnglish
Korean
Published 30.08.2021
Subjects
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
PHYSICS
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Summary:According to the present disclosure, a system-on-chip includes: a first memory configured to store first data; a second memory; and a data processing circuit configured to divide the first data obtained from the first memory into a plurality of pieces of division data, assign a plurality of tags to the plurality of pieces of division data, each of the plurality of tags including a coordinate value for a corresponding piece of division data, obtain second data based on at least the first data and/or the plurality of tags for the plurality of pieces of division data, and provide an address and the second data, obtained based on the plurality of tags, to the second memory. Accordingly, a data padding operation can be efficiently performed. 본 개시에 따르면, 시스템 온 칩은, 제1 데이터를 저장하는 제1 메모리, 제2 메모리 및 제1 메모리로부터 수신되는 제1 데이터를 복수의 분할 데이터들로 분할하고, 복수의 분할 데이터들 각각에 좌표 값을 포함하는 태그를 할당하고, 제1 데이터 및/또는 복수의 분할 데이터들에 대한 복수의 태그들을 기초로 제2 데이터를 획득하고, 복수의 태그들을 기초로 생성되는 어드레스 및 제2 데이터를 제2 메모리에 제공하도록 구성되는 데이터 처리 회로를 포함할 수 있다.
Bibliography:Application Number: KR20200021128