SEMICONDUCTOR PACKAGE
Provided is a semiconductor package which comprises: a lower package including a first substrate, a first semiconductor chip mounted on the first substrate, and a first molding unit covering the first semiconductor chip on the first substrate; an interposer substrate stacked on the first semiconduct...
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| Main Authors | , , |
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| Format | Patent |
| Language | English Korean |
| Published |
24.06.2021
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| Subjects | |
| Online Access | Get full text |
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| Abstract | Provided is a semiconductor package which comprises: a lower package including a first substrate, a first semiconductor chip mounted on the first substrate, and a first molding unit covering the first semiconductor chip on the first substrate; an interposer substrate stacked on the first semiconductor chip; a support part disposed on one side of the first semiconductor chip and supporting the interposer substrate between the interposer substrate and the first substrate; a connection terminal connecting the interposer substrate and the first substrate; and an upper package mounted on the interposer substrate, wherein the upper package includes a second substrate, at least one second semiconductor chip mounted on the second substrate, and a second molding unit covering the second semiconductor chip on the second substrate. Therefore, the semiconductor package increases structural stability.
제 1 기판, 상기 제 1 기판 상에 실장되는 제 1 반도체 칩, 및 상기 제 1 기판 상에서 상기 제 1 반도체 칩을 덮는 제 1 몰딩부를 포함하는 하부 패키지, 상기 제 1 반도체 칩 상에 적층되는 인터포저 기판, 상기 제 1 반도체 칩의 일측에 배치되고, 상기 인터포저 기판과 상기 제 1 기판 사이에서 상기 인터포저 기판을 지지하는 지지부, 상기 인터포저 기판과 상기 제 1 기판을 연결하는 연결 단자, 및 상기 인터포저 기판 상에 실장되고, 제 2 기판, 상기 제 2 기판 상에 실장되는 적어도 하나의 제 2 반도체 칩, 및 상기 제 2 기판 상에서 상기 제 2 반도체 칩을 덮는 제 2 몰딩부를 포함하는 상부 패키지를 포함하는 반도체 패키지를 제공한다. |
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| AbstractList | Provided is a semiconductor package which comprises: a lower package including a first substrate, a first semiconductor chip mounted on the first substrate, and a first molding unit covering the first semiconductor chip on the first substrate; an interposer substrate stacked on the first semiconductor chip; a support part disposed on one side of the first semiconductor chip and supporting the interposer substrate between the interposer substrate and the first substrate; a connection terminal connecting the interposer substrate and the first substrate; and an upper package mounted on the interposer substrate, wherein the upper package includes a second substrate, at least one second semiconductor chip mounted on the second substrate, and a second molding unit covering the second semiconductor chip on the second substrate. Therefore, the semiconductor package increases structural stability.
제 1 기판, 상기 제 1 기판 상에 실장되는 제 1 반도체 칩, 및 상기 제 1 기판 상에서 상기 제 1 반도체 칩을 덮는 제 1 몰딩부를 포함하는 하부 패키지, 상기 제 1 반도체 칩 상에 적층되는 인터포저 기판, 상기 제 1 반도체 칩의 일측에 배치되고, 상기 인터포저 기판과 상기 제 1 기판 사이에서 상기 인터포저 기판을 지지하는 지지부, 상기 인터포저 기판과 상기 제 1 기판을 연결하는 연결 단자, 및 상기 인터포저 기판 상에 실장되고, 제 2 기판, 상기 제 2 기판 상에 실장되는 적어도 하나의 제 2 반도체 칩, 및 상기 제 2 기판 상에서 상기 제 2 반도체 칩을 덮는 제 2 몰딩부를 포함하는 상부 패키지를 포함하는 반도체 패키지를 제공한다. |
| Author | CHOI JAEWON KANG TAEWOO KIM SUNG BUM |
| Author_xml | – fullname: CHOI JAEWON – fullname: KIM SUNG BUM – fullname: KANG TAEWOO |
| BookMark | eNrjYmDJy89L5WQQDXb19XT293MJdQ7xD1IIcHT2dnR35WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgZGhgYG5mZGlkaOxsSpAgDkASF_ |
| ContentType | Patent |
| DBID | EVB |
| DatabaseName | esp@cenet |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Medicine Chemistry Sciences |
| DocumentTitleAlternate | 반도체 패키지 |
| ExternalDocumentID | KR20210076292A |
| GroupedDBID | EVB |
| ID | FETCH-epo_espacenet_KR20210076292A3 |
| IEDL.DBID | EVB |
| IngestDate | Fri Jul 19 14:28:30 EDT 2024 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English Korean |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-epo_espacenet_KR20210076292A3 |
| Notes | Application Number: KR20190167132 |
| OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210624&DB=EPODOC&CC=KR&NR=20210076292A |
| ParticipantIDs | epo_espacenet_KR20210076292A |
| PublicationCentury | 2000 |
| PublicationDate | 20210624 |
| PublicationDateYYYYMMDD | 2021-06-24 |
| PublicationDate_xml | – month: 06 year: 2021 text: 20210624 day: 24 |
| PublicationDecade | 2020 |
| PublicationYear | 2021 |
| RelatedCompanies | SAMSUNG ELECTRONICS CO., LTD |
| RelatedCompanies_xml | – name: SAMSUNG ELECTRONICS CO., LTD |
| Score | 3.317549 |
| Snippet | Provided is a semiconductor package which comprises: a lower package including a first substrate, a first semiconductor chip mounted on the first substrate,... |
| SourceID | epo |
| SourceType | Open Access Repository |
| SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| Title | SEMICONDUCTOR PACKAGE |
| URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210624&DB=EPODOC&locale=&CC=KR&NR=20210076292A |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSTZLsTQyT0vUNbC0MNM1MU401U1MTDbUTTIxsUxLSk00TUsEjUP6-pl5hJp4RZhGMDHkwPbCgM8JLQcfjgjMUcnA_F4CLq8LEINYLuC1lcX6SZlAoXx7txBbFzVo7xjYfzEzMlFzcbJ1DfB38XdWc3a29Q5S8wuCyAH77EaWRo7MDKyghjTopH3XMCfQvpQC5ErFTZCBLQBoXl6JEANTdr4wA6cz7O41YQYOX-iUN5AJzX3FIgyiwaBA8_dzCXUO8Q9SCHB09nZ0dxVlUHZzDXH20AWaHw_3Trx3ELJjjMUYWIAd_VQJBoVUI8uURGNge8vcOM3EMNXQAtjWAh1vZmyZBGyGmRtIMsjgM0kKv7Q0AxeIC1rmZGQiw8BSUlSaKgusUEuS5MDhAADqenTS |
| link.rule.ids | 230,309,786,891,25594,76903 |
| linkProvider | European Patent Office |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT4NAEJ7Uaqw3rTU-qjbRcCMWWKAciKELiFIeQWp6IwuFxGhsYzH-fQek2lNvm51ksjvJ7Mw3Ow-A20yZa6JaMH6ojRSeSEzmGcsEPiVEK9KcyQWr4pCerzhT8jSTZy14X9fC1H1Cv-vmiKhRGep7Wb_Xy_8gllnnVq7u0lfcWtzbsW5yDTpG_KKIhDPHuhUGZkA5SnU34vzol4aYXdREYwd2VQSFNVh6GVd1KctNo2Ifwl6I_D7KI2i9LbrQoevZa13Y95ovb1w22rc6ht5zJbTAN6c0DqJBaFDXeLB6cGNbMXV45J_8XSdxo83DSCfQRqCfn8IgF7U5k9DfUqWCCLkwQl-ram8maSm6YerwDPrbOJ1vJ19Dx4m9STJ59N0LOKhIVcqTSPrQLj-_8ks0rmV6VcvkB4V8d7w |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=SEMICONDUCTOR+PACKAGE&rft.inventor=CHOI+JAEWON&rft.inventor=KIM+SUNG+BUM&rft.inventor=KANG+TAEWOO&rft.date=2021-06-24&rft.externalDBID=A&rft.externalDocID=KR20210076292A |