3차원 메모리 장치에서 반도체 플러그의 결함을 감소시키기 위한 방법

• Main Authors: HE JIA, LIU FANDONG, XIA ZHILIANG, HUA WENYU, WU LINCHUN, PU YUEQIANG
• Format: Patent
• Language: Korean
• Published: 21.04.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

유전체 식각 정지층을 갖는 3D 메모리 장치 및 이를 형성하기 위한 방법의 실시예가 개시된다. 예에서, 3D 메모리 장치는 기판, 기판 상에 배치된 유전체 식각 정지층, 유전체 식각 정지층 상에 배치되고 복수의 인터리빙된 전도체층 및 유전체층을 포함하는 메모리 스택, 및 각각 메모리 스택을 통해 수직으로 연장되고 메모리 스트링의 바닥 부분에 선택적 에피 택셜 성장(SEG) 플러그를 포함하는 복수의 메모리 스트링을 포함한다. SEG 플러그는 기판 상에 배치된다. Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening. The method further includes forming a memory stack comprising a plurality of interleaved dielectric layers and conductor layers by replacing the sacrificial layers in the dielectric stack with the conductor layers.