SYSTEM-ON-CHIP HAVING MERGED FRC AND VIDEO CODEC AND FRAME RATE CONVERTING METHOD THEREOF

• Main Authors: AN JEEHOON, BYUN JUWON
• Format: Patent
• Language: English; Korean
• Published: 01.06.2020
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

The present invention relates to a system-on-chip having a merged frame rate converter and a video codec, and a frame rate conversion method thereof. According to an embodiment of the present invention, the system-on-chip having the merged frame rate converter and the video codec comprises: a motion estimation part calculating a motion vector of an input image; a motion compensation part compensating a motion of the input image by using the motion vector; and a parameter generator which controls to filter motion-compensated image data by transmitting the same to a deblocking filter of the video codec. Therefore, the system-on-chip can reduce a chip area without deteriorating the performance thereof and reduce costs of configuring the system-on-chip. 본 발명의 실시 예에 따른 비디오 코덱을 포함하는 시스템 온 칩은, 입력 영상의 움직임 벡터를 계산하는 움직임 추정부, 상기 움직임 벡터를 사용하여 상기 입력 영상의 움직임을 보상하는 움직임 보상부, 그리고 상기 움직임이 보상된 이미지 데이터를 상기 비디오 코덱의 디블록킹 필터로 전달하여 필터링하도록 제어하는 파라미터 생성기를 포함한다.