USING MASK LAYERS TO FACILITATE THE FORMATION OF SELF-ALIGNED CONTACTS AND VIAS

• Main Authors: TSAI KUO CHIANG, SU FU HSIANG, CHEN JYH HUEI, CHEN YI JU, YU KE JING
• Format: Patent
• Language: English; Korean
• Published: 06.05.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A source/drain area is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a side wall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over the source/drain area or the gate structu...