RESISTIVE MEMORY DEVICE INCLUDING REFERENCE CELL AND OPERATING METHOD THEREOF

According to an exemplary embodiment of the present disclosure, provided is a resistive memory device, which comprises: a first column including memory cells; a cell array including a second column including off cells, and a third column including reference cells; a read circuit configured to receiv...

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Bibliographic Details
Main Author ANTONYAN ARTUR
Format Patent
LanguageEnglish
Korean
Published 20.11.2019
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:According to an exemplary embodiment of the present disclosure, provided is a resistive memory device, which comprises: a first column including memory cells; a cell array including a second column including off cells, and a third column including reference cells; a read circuit configured to receive a first read voltage by providing a first read current to the first column, and to receive a reference voltage by providing a second read current to the third column; and a compensation circuit configured to provide a second read voltage corresponding to the first read voltage to the second column, and to draw a compensation current corresponding to a current by the second column and the second read voltage from the second read current. 저항성 메모리 장치는, 본 개시의 예시적 실시예에 따라, 메모리 셀들을 포함하는 제1 컬럼, 오프 셀들을 포함하는 제2 컬럼 및 레퍼런스 셀들을 포함하는 제3 컬럼을 포함하는 셀 어레이, 제1 컬럼에 제1 독출 전류를 제공함으로써 제1 독출 전압을 수신하고, 제3 컬럼에 제2 독출 전류를 제공함으로써 레퍼런스 전압을 수신하도록 구성된 독출 회로, 및 제1 독출 전압에 대응하는 제2 독출 전압을 제2 컬럼에 제공하고, 제2 컬럼 및 제2 독출 전압에 의한 전류에 대응하는 보상 전류를 제2 독출 전류로부터 인출하도록 구성된 보상 회로를 포함할 수 있다.
Bibliography:Application Number: KR20180053928