FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package according to an embodiment of the present invention includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant sealing the semiconductor chip, and an electromagnetic wav...

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Bibliographic Details
Main Authors HAN MI JA, PARK DAE HYUN, LEE SANG JONG, LEE SEONG HWAN
Format Patent
LanguageEnglish
Korean
Published 13.11.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A fan-out semiconductor package according to an embodiment of the present invention includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant sealing the semiconductor chip, and an electromagnetic wave shielding layer disposed on the semiconductor chip and including a plurality of degas holes. The electromagnetic wave shielding layer may include a first region and a second region having different densities of the degas holes. The density of the degas holes in the first region is higher than the density of the degas holes in the second region. It is possible to remove gas effectively. 본 발명의 일 실시 형태에 따른 팬-아웃 반도체 패키지는 절연층과 재배선층을 포함하는 연결부재와, 상기 연결부재 상에 배치된 반도체칩과, 상기 반도체칩을 봉합하는 봉합재 및 상기 반도체칩 상에 배치되며 복수의 디가스 홀을 포함하는 전자파 차폐층을 포함하며, 상기 전자파 차폐층은 상기 디가스 홀의 밀도가 서로 다른 제1 영역과 제2 영역을 포함하되 상기 제1 영역이 상기 제2 영역보다 상기 디가스 홀의 밀도가 높은 형태이다.
Bibliography:Application Number: KR20180051914