ETCH STOP LAYER FOR SEMICONDUCTOR DEVICES
The present invention relates to a semiconductor device. According to the present invention, the semiconductor device comprises: a substrate; a first conductive feature over a portion of the substrate; and an etch stop layer over the first conductive feature and the substrate. The etch stop layer in...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English Korean |
Published |
25.09.2019
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | The present invention relates to a semiconductor device. According to the present invention, the semiconductor device comprises: a substrate; a first conductive feature over a portion of the substrate; and an etch stop layer over the first conductive feature and the substrate. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further comprises a dielectric layer over the etch stop layer and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and is electrically connected to the first conductive feature.
반도체 디바이스는 기판, 기판의 일부분 위의 제1 도전성 피쳐, 및 제1 도전성 피쳐와 기판 위의 에칭 스탑 층을 포함한다. 에칭 스탑 층은 실리콘 함유 유전체(SCD, silicon-containing dielectric) 층 및 SCD 층 위의 금속 함유 유전체 (MCD, metal-containing dielectric) 층을 포함한다. 반도체 디바이스는, 에칭 스탑 층 위의 유전체 층, 및 유전체 층 내의 제2 도전성 피쳐를 더 포함한다. 제2 도전성 피쳐는 에칭 스탑 층을 관통하며, 제1 도전성 피쳐에 전기적으로 연결된다. |
---|---|
Bibliography: | Application Number: KR20190113738 |