CLOCK MONITORING CIRCUIT

A clock monitoring circuit includes a sampling circuit for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit for counting the number of the monitoring target clocks sampled by the sampling circuit to a predetermined level; and a second counter circu...

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Bibliographic Details
Main Authors CHOI YOUNG JAE, PARK MYEONG JAE
Format Patent
LanguageEnglish
Korean
Published 04.07.2019
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:A clock monitoring circuit includes a sampling circuit for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit for counting the number of the monitoring target clocks sampled by the sampling circuit to a predetermined level; and a second counter circuit for counting the number of the sampling circuits sampled. The status of a clock in a circuit can be directly monitored. 클럭 모니터링 회로는, 모니터링 대상 클럭을 샘플링 클럭에 동기해 샘플링하는 샘플링 회로; 상기 샘플링 회로에 의해 상기 모니터링 대상 클럭이 미리 설정된 레벨로 샘플링된 횟수를 카운팅하기 위한 제1카운터 회로; 및 상기 샘플링 회로의 샘플링 횟수를 카운팅하기 위한 제2카운터 회로를 포함할 수 있다.
Bibliography:Application Number: KR20170179850