TRANSISTOR AND PREPARATION METHOD THEREOF

The present invention relates to a transistor comprising: a first gate; a first insulating layer formed on the first gate; a channel layer formed on the first insulating layer; a first electrode located on a first region of the channel layer; and a second electrode disposed on a second region spaced...

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Bibliographic Details
Main Authors MINKYU JOO, JIN YOUNGJO, LEE YOUNGHEE
Format Patent
LanguageEnglish
Korean
Published 09.05.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present invention relates to a transistor comprising: a first gate; a first insulating layer formed on the first gate; a channel layer formed on the first insulating layer; a first electrode located on a first region of the channel layer; and a second electrode disposed on a second region spaced apart from the first region on the channel layer, wherein the channel layer includes graphene and semiconductor material layers and the graphene and semiconductor material layers are laminated to form a heterojunction interface. 제 1 게이트; 상기 제 1 게이트 상에 형성된 제 1 절연층; 상기 제 1 절연층 상에 형성된 채널층; 상기 채널층의 제 1 영역 상에 위치하는 제 1 전극; 및 상기 채널층의 상기 제 1 영역과 이격된 제 2 영역 상에 위치하는 제 2 전극; 을 포함하고, 상기 채널층은 그래핀 및 반도체 물질층을 포함하며, 상기 그래핀 및 상기 반도체 물질층은 적층되어 이종접합 계면을 형성하는 것인, 트랜지스터에 관한 것이다.
Bibliography:Application Number: KR20170142557