SEMICONDUCTOR DEVICE

The polysilicon resistance has a large resistance variation rate after the completion of a mold package process. In order to enable high-precision trimming, the implementation of resistance hardly influenced by stress generated in a substrate by the mold package process is desired. Resistor elements...

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Bibliographic Details
Main Authors HASHIMOTO CHIEMI, TSUNENO KATSUMI, YAYAMA KOSUKE, MATSUZAKI TOMOKAZU
Format Patent
LanguageEnglish
Korean
Published 04.01.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The polysilicon resistance has a large resistance variation rate after the completion of a mold package process. In order to enable high-precision trimming, the implementation of resistance hardly influenced by stress generated in a substrate by the mold package process is desired. Resistor elements are formed on a plurality of wiring layers, and the resistor elements have a repeating pattern of a first conductive layer (510) formed on a first wiring layer, a second conductive layer (52) formed on a second wiring layer, and an interlayer conductive layer (53) connecting the first conductive layer (51) and second conductive layer (52). 다결정 실리콘 저항은 몰드 패키지 프로세스 종료 후의 저항 변동률이 크다. 고정밀도의 트리밍을 가능하게 하기 위해, 몰드 패키지 프로세스에 의해 기판에 발생하는 응력의 영향을 거의 받지 않는 저항의 실현이 요망된다. 저항 소자는 복수의 배선층에 형성되며, 제1 배선층에 형성되는 제1 도전층(51), 제2 배선층에 형성되는 제2 도전층(52) 및 제1 도전층(51)과 제2 도전층(52)을 접속하는 층간 도전층(53)의 반복 패턴을 갖는다.
Bibliography:Application Number: KR20180065959