FAN-OUT SEMICONDUCTOR PACKAGE

• Main Authors: KO, TAE HO, KIM, YEONG A, BYUN, DAE JUNG, KIM, EUN SIL, LEE, DOO HWAN
• Format: Patent
• Language: English; Korean
• Published: 12.10.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

본 개시는 관통홀을 갖는 제1연결부재, 상기 제1연결부재의 관통홀에 배치되며 접속패드가 배치된 활성면 및 상기 활성면의 반대측에 배치된 비활성면을 갖는 반도체칩, 상기 제1연결부재 및 상기 반도체칩의 비활성면의 적어도 일부를 봉합하는 봉합재, 상기 제1연결부재 및 상기 반도체칩의 활성면 상에 배치된 제2연결부재, 및 상기 봉합재 상에 배치된 보강층을 포함하며, 상기 제1연결부재 및 상기 제2연결부재는 각각 상기 반도체칩의 접속패드와 전기적으로 연결된 재배선층을 포함하는, 팬-아웃 반도체 패키지에 관한 것이다. A fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.