SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• Main Authors: KUO CHIEN LI, LIN HSIN CHIH, CHEN LIEH CHUAN, HUANG KUN MING, CHU PO TAO, YOU JHENG SHENG, WANG SHEN PING
• Format: Patent
• Language: English; Korean
• Published: 08.03.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A semiconductor device includes a first III-V compound layer which is formed on a substrate, a second III-V compound layer which is formed on the first III-V compound layer, wherein the material of the first III-V compound layer is different from the material of the second III-V compound layer, a gate metal stack which is formed on the second III-V compound layer, a source contact and a drain contact which are arranged on a side facing the gate metal stack, a gate electric field plate which is arranged between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer which is formed on the source contact and the drain contact, and an etching stop layer which is formed on the ARC layer. Accordingly, the present invention can prevent a metal loss of an ohmic contact for a process of defining the gate electric field plate. 반도체 디바이스는, 기판 상의 제1 Ⅲ-Ⅴ 화합물 층, 상기 제1 Ⅲ-Ⅴ 화합물 층 상의 제2 Ⅲ-Ⅴ 화합물 층 - 상기 제1 Ⅲ-Ⅴ 화합물 층의 재료는 상기 제2 Ⅲ-Ⅴ 화합물 층의 재료와 상이함 - , 제2 Ⅲ-Ⅴ 화합물 층 상에 배치된 게이트 금속 스택, 게이트 금속 스택의 대향 측에 배치된 소스 컨택 및 드레인 컨택, 게이트 금속 스택과 드레인 컨택 사이에 배치된 게이트 전계판, 소스 컨택 및 드레인 컨택 상에 형성된 반사 방지 코팅(ARC) 층, 및 ARC 층 상에 형성된 에칭 정지 층을 포함한다.