INSTRUCTIONS TO MARK BEGINNING AND END OF NON TRANSACTIONAL CODE REGION REQUIRING WRITE BACK TO PERSISTENT STORAGE

A processor written in the present invention includes an interface to a nonvolatile random access memory and a logic circuit. The logic circuit is to identify a cache line modified by a transaction considering the nonvolatile random access memory as a permanent storing place of the transaction. In a...

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Bibliographic Details
Main Author WILLHALM THOMAS
Format Patent
LanguageEnglish
Korean
Published 10.11.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor written in the present invention includes an interface to a nonvolatile random access memory and a logic circuit. The logic circuit is to identify a cache line modified by a transaction considering the nonvolatile random access memory as a permanent storing place of the transaction. In addition, the logic circuit is also to identify cache lines modified by a software process different from the transaction regarding the nonvolatile random access memory as the permanent storing place. 본원에 기재되는 프로세서는 비휘발성 랜덤 액세스 메모리와 로직 회로로의 인터페이스를 갖는다. 로직 회로는 비휘발성 랜덤 액세스 메모리를 트랜잭션의 영구 저장소로 보는 트랜잭션에 의해 수정되는 캐시 라인들을 식별한다. 로직 회로는 또한 비휘발성 랜덤 액세스 메모리를 영구 저장소로 보는 트랜잭션과는 다른 소프트웨어 프로세스에 의해 수정되는 캐시 라인들을 식별한다.
Bibliography:Application Number: KR20160144211