SEMICONDUCTOR DIEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device and a manufacturing method thereof are provided. According to an embodiment, the manufacturing method of the semiconductor device comprises the following steps of: preparing a substrate having a protruding active pattern; forming a recess region in the active pattern by elimin...
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Main Authors | , , , , , , , |
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Format | Patent |
Language | English Korean |
Published |
20.10.2016
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Subjects | |
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Abstract | A semiconductor device and a manufacturing method thereof are provided. According to an embodiment, the manufacturing method of the semiconductor device comprises the following steps of: preparing a substrate having a protruding active pattern; forming a recess region in the active pattern by eliminating a portion of the active pattern; forming source/drain patterns on the recess region of the active pattern wherein the source/drain patterns include silicon-germanium; and forming a capping pattern on the source/drain patterns. The step of forming the capping pattern can includes a step of eliminating the germanium included in the source/drain patterns.
반도체 소자 및 그 제조방법에 제공된다. 실시예들에 따른 반도체 소자 제조방법은 돌출된 활성 패턴을 갖는 기판을 준비하는 것; 상기 활성 패턴의 일부를 제거하여, 상기 활성 패턴에 리세스 영역을 형성하는 것; 상기 활성 패턴의 상기 리세스 영역 상에 소스/드레인 패턴을 형성하되, 상기 소스/드레인 패턴은 실리콘-게르마늄을 포함하는 것; 및 상기 소스/드레인 패턴 상에 캐핑 패턴을 형성하는 것을 포함할 수 있다. 상기 캐핑 패턴을 형성하는 것은 상기 소스/드레인 패턴에 포함된 게르마늄을 제거하는 것을 포함할 수 있다. |
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AbstractList | A semiconductor device and a manufacturing method thereof are provided. According to an embodiment, the manufacturing method of the semiconductor device comprises the following steps of: preparing a substrate having a protruding active pattern; forming a recess region in the active pattern by eliminating a portion of the active pattern; forming source/drain patterns on the recess region of the active pattern wherein the source/drain patterns include silicon-germanium; and forming a capping pattern on the source/drain patterns. The step of forming the capping pattern can includes a step of eliminating the germanium included in the source/drain patterns.
반도체 소자 및 그 제조방법에 제공된다. 실시예들에 따른 반도체 소자 제조방법은 돌출된 활성 패턴을 갖는 기판을 준비하는 것; 상기 활성 패턴의 일부를 제거하여, 상기 활성 패턴에 리세스 영역을 형성하는 것; 상기 활성 패턴의 상기 리세스 영역 상에 소스/드레인 패턴을 형성하되, 상기 소스/드레인 패턴은 실리콘-게르마늄을 포함하는 것; 및 상기 소스/드레인 패턴 상에 캐핑 패턴을 형성하는 것을 포함할 수 있다. 상기 캐핑 패턴을 형성하는 것은 상기 소스/드레인 패턴에 포함된 게르마늄을 제거하는 것을 포함할 수 있다. |
Author | LEE, KWAN HEUM PARK, JAE YOUNG LEE, DONG HUN YOON, JI EON LEE, CHO EUN YOO, JEONG HO KIM, JIN BUM KOO, BON YOUNG |
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SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | SEMICONDUCTOR DIEVICES AND METHODS OF MANUFACTURING THE SAME |
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