INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

An integrated circuit device comprises first and second fin-type active regions having different conductive type channel regions wherein a first device isolation layer covers both sidewalls of the first fin-type active region, and a second device isolation layer covers both sidewalls of the second f...

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Bibliographic Details
Main Authors KIM, HYUN JO, RHEE, HWA SUNG, LEE, YOON SEOK, JEONG, HEE DON, JEONG, BO CHEOL, CHUNG, JAE YUP, PARK, SE WAN
Format Patent
LanguageEnglish
Korean
Published 01.09.2016
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Summary:An integrated circuit device comprises first and second fin-type active regions having different conductive type channel regions wherein a first device isolation layer covers both sidewalls of the first fin-type active region, and a second device isolation layer covers both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structures. 집적회로 소자는 서로 다른 도전형 채널 영역을 가지는 제1 핀형 활성 영역의 양 측벽을 덮는 제1 소자분리막 및 제2 소자분리막을 포함한다. 제1 소자분리막과 제2 소자분리막은 서로 다른 적층 구조를 가진다. 집적회로 소자를 제조하기 위하여 제1 핀형 활성 영역 및 제2 핀형 활성 영역을 형성한 후, 제1 핀형 활성 영역의 양 측벽을 덮는 제1 소자분리막과 제2 핀형 활성 영역의 양 측벽을 덮는 제2 소자분리막을 형성한다. 제1 소자분리막 및 제2 소자분리막은 서로 다른 적층 구조를 가지도록 형성한다.
Bibliography:Application Number: KR20150025919