SEMICONDUCTOR PACKAGE
A semiconductor package according to the embodiment of the present invention may include a semiconductor chip; a connection device arranged on one side of the semiconductor ship; an insulating layer which covers the lower surface of the semiconductor chip and the lower surface of the connection devi...
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| Main Authors | , , , , |
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| Format | Patent |
| Language | English Korean |
| Published |
13.07.2016
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A semiconductor package according to the embodiment of the present invention may include a semiconductor chip; a connection device arranged on one side of the semiconductor ship; an insulating layer which covers the lower surface of the semiconductor chip and the lower surface of the connection device; a molding layer which is arranged on the insulating layer and covers one surface of the semiconductor chip, and the upper surface and both sides of the connection device; a line which is arranged in the insulating layer and is electrically connected to the semiconductor chip and the connection device; and an external terminal which is arranged on the insulating layer, and is electrically connected to the line. So, the reliability of the semiconductor package can be improved.
본 발명의 실시예에 따른 반도체 패키지는 반도체 칩, 상기 반도체 칩의 일측에 배치된 연결장치, 상기 반도체 칩의 하부면 및 상기 연결장치의 하부면을 덮는 절연막, 상기 절연막 상에 배치되며, 상기 반도체 칩의 하부면 및 상기 연결장치의 하부면을 덮는 절연막, 상기 절연막 상에 배치되며, 상기 반도체 칩의 일측면, 상기 연결장치의 상부면 및 양 측면들을 덮는 몰딩막, 상기 절연막 내에 배치되며, 상기 반도체 칩 및 상기 연결장치와 전기적으로 연결되는 배선, 및 상기 절연막 상에 배치되며, 상기 배선과 전기적으로 연결되는 외부 단자를 포함할 수 있다. |
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| AbstractList | A semiconductor package according to the embodiment of the present invention may include a semiconductor chip; a connection device arranged on one side of the semiconductor ship; an insulating layer which covers the lower surface of the semiconductor chip and the lower surface of the connection device; a molding layer which is arranged on the insulating layer and covers one surface of the semiconductor chip, and the upper surface and both sides of the connection device; a line which is arranged in the insulating layer and is electrically connected to the semiconductor chip and the connection device; and an external terminal which is arranged on the insulating layer, and is electrically connected to the line. So, the reliability of the semiconductor package can be improved.
본 발명의 실시예에 따른 반도체 패키지는 반도체 칩, 상기 반도체 칩의 일측에 배치된 연결장치, 상기 반도체 칩의 하부면 및 상기 연결장치의 하부면을 덮는 절연막, 상기 절연막 상에 배치되며, 상기 반도체 칩의 하부면 및 상기 연결장치의 하부면을 덮는 절연막, 상기 절연막 상에 배치되며, 상기 반도체 칩의 일측면, 상기 연결장치의 상부면 및 양 측면들을 덮는 몰딩막, 상기 절연막 내에 배치되며, 상기 반도체 칩 및 상기 연결장치와 전기적으로 연결되는 배선, 및 상기 절연막 상에 배치되며, 상기 배선과 전기적으로 연결되는 외부 단자를 포함할 수 있다. |
| Author | CHOI, IN HO SONG, JIK HO KIM, JAE CHOON UMEMOTO MITSUO KIM, DONG HAN |
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| RelatedCompanies | SAMSUNG ELECTRONICS CO., LTD |
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| Snippet | A semiconductor package according to the embodiment of the present invention may include a semiconductor chip; a connection device arranged on one side of the... |
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| SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| Title | SEMICONDUCTOR PACKAGE |
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