CIRCUIT AND METHOD FOR MONOLITHIC STACKED INTEGRATED CIRCUIT TESTING

A monolithic stacked integrated circuit (IC) is equipped with a known-good-layer (KGL) path delay test circuit, and at least a portion of a critical path in one of the layers of the IC. The test circuit includes a plurality of inputs, outputs, flip-flops coupled to a portion of the critical path, an...

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Bibliographic Details
Main Author GOEL SANDEEP KUMAR
Format Patent
LanguageEnglish
Korean
Published 26.03.2015
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A monolithic stacked integrated circuit (IC) is equipped with a known-good-layer (KGL) path delay test circuit, and at least a portion of a critical path in one of the layers of the IC. The test circuit includes a plurality of inputs, outputs, flip-flops coupled to a portion of the critical path, and multiplexers coupled to the flip-flops and to a second layer of the IC. The test circuit further includes control elements, and the path delay testing of the IC can be conducted on a layer-by-layer basis accordingly.
Bibliography:Application Number: KR20130152918