CIRCUIT AND METHOD FOR MONOLITHIC STACKED INTEGRATED CIRCUIT TESTING

A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of the layers of the IC. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circ...

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Bibliographic Details
Main Author GOEL SANDEEP KUMAR
Format Patent
LanguageEnglish
Korean
Published 25.03.2015
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of the layers of the IC. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the IC may be conducted on a layer-by-layer basis.
Bibliography:Application Number: KR20140114123