METHOD FOR INTEGRATED CIRCUIT PATTERNING

• Main Authors: LIU RU GUN, LEE CHUNG JU, SHIEH MING FENG, BAO TIEN I, HSIEH HUNG CHANG, SHUE SHAU LIN
• Format: Patent
• Language: English; Korean
• Published: 11.03.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The present invention relates to a method for patterning integrated circuit in order to solve problems on both a CD flexible budget and an overlay budget of a cut pattern, and an overlay error effect in a multi-patterning. A method for forming a target pattern comprises the steps of: forming a first trench inside a substrate with a cut mask; forming a plurality of first lines on the substrate with a first main mask which is overlapped with the first trench and includes at least one line cut into at least two lines by the first trench accordingly; forming a spacer layer on the substrate and the first lines, and on side walls of the first lines; forming a plurality of second trenches collectively by a patterned material layer and the spacer layer as the patterned material layer is formed on the spacer layer with a second mask; removing at least a part of the spacer layer in order to expose the first lines; and removing the first lines, which results in a patterned spacer layer on the substrate.