MOS DEVICES WITH NON-UNIFORM P-TYPE IMPURITY PROFILE

The present invention is provided to improve a performance of an MOS device. An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack....

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Bibliographic Details
Main Authors SUNG HSUEH CHANG, LI KUN MU, LI CHII HORNG, LEE TZE LIANG, KWOK TSZ MEI
Format Patent
LanguageEnglish
Korean
Published 26.01.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present invention is provided to improve a performance of an MOS device. An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.
Bibliography:Application Number: KR20140088284