THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME

• Main Authors: WON, GYU SIK, JANG, HUN, KANG, GYU TAE, LEE, SUL
• Format: Patent
• Language: English; Korean
• Published: 02.01.2015
• Subjects: BASIC ELECTRIC ELEMENTS; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL ANALOGUE/DIGITAL CONVERTERS; OPTICAL LOGIC ELEMENTS; OPTICS; PHYSICS; SEMICONDUCTOR DEVICES; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF

The present invention relates to a thin film transistor array substrate and a manufacturing method thereof, capable of reducing capacitance generated between a vertical gate wire and a data wire. The thin film transistor array substrate according to the present invention includes a horizontal gate wire and a gate electrode which are formed on the substrate, a gate insulation layer which covers the horizontal gate wire and the gate electrode on the substrate and includes a gate contact hole to expose the horizontal gate wire, a vertical gate wire which is formed on the gate insulation layer to cross the horizontal gate wire, a semiconductor layer which is formed on the gate insulation layer to overlap the gate electrode, a source electrode and a drain electrode which are separately arranged on the semiconductor layer, a first protection layer which is formed on the gate insulation layer to expose the gate contact hole and a part of the vertical gate wire, the source electrode, and the drain electrode, a pixel electrode which is formed on the first protection layer and is connected to the drain electrode which is exposed by the first protection layer, a source connection pattern which is connected to the source electrode which is exposed by the first protection layer, a gate connection pattern which connects the horizontal gate wire which is exposed through the gate contact hole and the vertical gate wire which is exposed by the first protection layer, and a data wire which is formed on the source connection pattern.