APPARATUS AND METHOD FOR GENERATING TEST CASE FOR PROCESSOR VERIFICATION AND, VERIFICATION APPARATUS

The present invention relates to a device to create test cases which do not overlap to verify a processor. According to an embodiment, the device may include: a constrained condition generation unit which defines a plurality of constrained verification spaces in a total verification space and genera...

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Bibliographic Details
Main Authors CHO, YOUNG CHUL, JEONG, SEONG HOON, JUNG, JIN SAE, HAN YEN JO, CHUNG, MOO KYOUNG, SHIM, HEE JUN
Format Patent
LanguageEnglish
Korean
Published 30.10.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The present invention relates to a device to create test cases which do not overlap to verify a processor. According to an embodiment, the device may include: a constrained condition generation unit which defines a plurality of constrained verification spaces in a total verification space and generates a constrained condition description for each of the constrained verification spaces; and a test case generation unit which generates test cases using the constrained condition descriptions.
Bibliography:Application Number: KR20130044434