PROCESSORS, METHODS, AND SYSTEMS TO IMPLEMENT PARTIAL REGISTER ACCESSES WITH MASKED FULL REGISTER ACCESSES

A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand which is wider than and includes the first...

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Bibliographic Details
Main Authors GUY BUFORD MASON, SOTOUDEH SEYED YAHYA, GROCHOWSKI EDWARD T
Format Patent
LanguageEnglish
Korean
Published 08.10.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand which is wider than and includes the first narrower source operand, and indicates a wider destination operand which is wider than and includes the narrower destination operand. A packed data operation mask is generated and includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements which corresponds to the result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masked out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.
Bibliography:Application Number: KR20140037312