INSTRUCTIONS AND LOGIC TO PROVIDE ADVANCED PAGING CAPABILITIES FOR SECURE ENCLAVE PAGE CACHES

• Main Authors: MCKEEN FRANCIS X, NEIGER GILBERT, RAPPOPORT RINAT, WOOD WILLIAM COLIN, JOHNSON SIMON P, IVANOV ANTON, ANATI ITTAI, SHANBHOGUE VEDVYAS, ROZAS CARLOS V, RODGERS SCOTT DION, GOLDSMITH MICHAEL A, SMITH WESLEY H, SCARLATA VINCENT R, LESLIE HURD REBEKAH M, HUNTLEY BARRY E, ALEXANDROVICH ILYA, BERENZON ALEX, SAVAGAONKAR UDAY R
• Format: Patent
• Language: English; Korean
• Published: 08.10.2014
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, and a cache to store secure data for a shared page address allocated to a secure enclave and accessible by the hardware threads. A decode stage decodes a first instruction specifying the shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for one of the first and second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying the secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, the execution units decreasing the recorded number of hardware threads when any of the hardware threads exits the secure enclave.