VOLTAGE ASSISTED STT-MRAM WRITING SCHEME
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which includes a magnetic element. The magnetic element according to the embodiment of the present invention includes a reference layer, a free layer, a barrier layer which is loca...
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Format | Patent |
Language | English Korean |
Published |
06.08.2014
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Online Access | Get full text |
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Abstract | The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which includes a magnetic element. The magnetic element according to the embodiment of the present invention includes a reference layer, a free layer, a barrier layer which is located between the reference layer and the reference layer, a first electrode, an insulation layer which is located between the first electrode and the free layer, and a second electrode which is connected to the side of the free layer. According to the present invention, a small amount of currents are used and an error rate is reduced. |
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AbstractList | The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which includes a magnetic element. The magnetic element according to the embodiment of the present invention includes a reference layer, a free layer, a barrier layer which is located between the reference layer and the reference layer, a first electrode, an insulation layer which is located between the first electrode and the free layer, and a second electrode which is connected to the side of the free layer. According to the present invention, a small amount of currents are used and an error rate is reduced. |
Author | ONG ADRIAN E NIKITIN VLADIMIR KROUNBI MOHAMAD TOWFIK |
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Snippet | The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which includes a magnetic element. The... |
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Title | VOLTAGE ASSISTED STT-MRAM WRITING SCHEME |
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