METHOD AND SYSTEM FOR DESIGNING 3D SEMICONDUCTOR PACKAGE

Provided is a method for designing a 3D semiconductor package, comprising the steps of providing a first layout parameter for a plurality of first terminals included in a first package, a second layout parameter for a plurality of second terminals included in a second package at an upper part or a l...

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Bibliographic Details
Main Authors LEE, TAE HEON, HWANG, BO SUN, YUN, SUNG HEE, JEONG, JAE HOON, LEE, WON CHEOL, CHEON, YOUNG HOE
Format Patent
LanguageEnglish
Korean
Published 28.07.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Provided is a method for designing a 3D semiconductor package, comprising the steps of providing a first layout parameter for a plurality of first terminals included in a first package, a second layout parameter for a plurality of second terminals included in a second package at an upper part or a lower part of the first package, and a third layout parameter for a plurality of connection terminals which electrically connect the first package to the second package; obtaining a first wire connection layout between a first and a second terminal and the connection terminals by applying a first algorithm to the first to the third layout parameter; and obtaining a second wire connection layout between the first and the second terminal and the connection terminals by applying a second algorithm, different from the first algorithm, to the first wire connection layout.
Bibliography:Application Number: KR20130005996