3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH

A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device waf...

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Bibliographic Details
Main Authors LEE KEVIN J, KOTHARI HITEN, MA HANG SHING, BOHR MARK T, PELTO CHRISTOPHER M, SATTIRAJU SESHU V, YEOH ANDREW W
Format Patent
LanguageEnglish
Korean
Published 04.07.2014
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
Bibliography:Application Number: KR20147014223