REDUCING POWER CONSUMPTION IN A FUSED MULTIPLY-ADD (FMA) UNIT RESPONSIVE TO INPUT DATA VALUES

• Main Authors: HICKMANN BRIAN J, BRADFORD DENNIS R, FLETCHER THOMAS D
• Format: Patent
• Language: English; Korean
• Published: 09.05.2014
• Subjects: CALCULATING; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; PHYSICS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

In an embodiment, a fused multiply-add (FMA) circuit receives a plurality of input data values to perform an FMA instruction related with the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic which receives the input data values and reduces switching activity to reduce power consumption of one or more components of the circuit based on a value of one or more input data values. Other embodiments are described and claimed.