A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE STRUCTURE

• Main Authors: CAO GUOHAO, PU XIANYONG, YANG GUANGLI, WANG MING
• Format: Patent
• Language: English; Korean
• Published: 12.03.2014
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The present invention provides a semiconductor element structure manufacturing method including a step of providing a substrate including an activation area and an isolation area (a first gate electrode structure is formed in the top of the activation area, a second gate electrode structure is formed in the top of the isolation area as a dummy gate electrode structure, and a spacer structure is formed at both sides off the first structure and both sides of the second structure), a step of removing the spacer structure placed at both sides of the second gate electrode structure by partially etching it, a step of forming an inner interconnection material layer on the top of the substrate and the first and second electrode structures, a step of forming an inner interconnection layer electrically connected to the second gate electrode structure and electrically isolated from the first gate electrode structure by wholly removing the inner interconnection material layer on the first gate electrode structure, and a step of forming an source/drain area contact hole on the inner interconnection layer. According to the method of the invention, a gap between a gate electrode structure and an isolation structure can be made so the size of a semiconductor element can be reduced and then a use rate of a semiconductor chip is improved and semiconductor manufacturing cost can be reduced. [Reference numerals] (S101) Provide a substrate on which a first and second gate electrode structures and a spacer structure placed at both sides of the first and second gate electrode structures are formed; (S102) Partially remove the spacer structure placed at both sides of the second gate electrode structure at least; (S103) Form an inner interconnection material layer; (S104) Form an inner interconnection layer electrically isolated from the first gate electrode structure and electrically connected to the second gate electrode structure; (S105) Form a source/drain area contact hole on the inner interconnection layer