ZERO CYCLE LOAD

The present invention includes a system and a method for reducing the latency of load operations. The load command language in which a register renaming unit within a processor is decoded to determine the conversion of the cycle load operation with the agent whether it is fit for the conversion or n...

Full description

Saved in:
Bibliographic Details
Main Authors MYLIUS JOHN H, BLASCO ALLUE CONRADO, WILLIAMS III GERARD R
Format Patent
LanguageEnglish
Korean
Published 24.12.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:The present invention includes a system and a method for reducing the latency of load operations. The load command language in which a register renaming unit within a processor is decoded to determine the conversion of the cycle load operation with the agent whether it is fit for the conversion or not. The physical register identifier associated with the source operand of the dependence store instruction and the control logic assigned to the destination location operand of the load command language are allocated. Moreover, a register renaming unit marks the load command language to prevent the load command language reading data associated with the source operand of the store instruction to be decoded from the memory. Due to the reproduction of the renaming, this data can be transmitted to newer instructions which are more dependent on the load command language from the physical register file. [Reference numerals] (100) Computer system;(110) Microprocessor;(112) Processor core;(114) Physical registers;(116) Cash memory subsystem;(118) Interface logic;(120) Memory controller;(122) Memory bus;(130) Disk memory;(150a,150b) Peripherals
Bibliography:Application Number: KR20130068008