SEMICONDUCTOR MEMORY DEVICE

The present invention provides a loadless 4T-SRAM configured from a vertical transistor SGT, the loadless 4T-SRAM having a small SRAM cell area. A stick-type memory cell configured by using four MOS transistors, wherein: the MOS transistors are SGTs which are formed on a bulk substrate and of which...

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Bibliographic Details
Main Authors ARAI SHINTARO, MASUOKA FUJIO
Format Patent
LanguageEnglish
Korean
Published 30.10.2013
Subjects
ELECTRICITY
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Summary:The present invention provides a loadless 4T-SRAM configured from a vertical transistor SGT, the loadless 4T-SRAM having a small SRAM cell area. A stick-type memory cell configured by using four MOS transistors, wherein: the MOS transistors are SGTs which are formed on a bulk substrate and of which the drain, gate, and source are arranged in a perpendicular direction; the gate of an access transistor functioning as a wide line is shared by multiple cells that are adjacent to one another in the horizontal direction; and one contact to the wide line is formed per multiple cells. As a consequence, it is possible to provide a CMOS-type loadless 4T-SRAM having an extremely small memory cell area.
Bibliography:Application Number: KR20137021568