METHOD TO OPTIMIZE AND REDUCE INTEGRATED CIRCUIT, PACKAGE DESIGN, AND VERIFICATION CYCLE TIME

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Bibliographic Details
Main Authors ZANG RUEY KAE, LANE RYAN D
Format Patent
LanguageEnglish
Korean
Published 27.06.2013
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Bibliography:Application Number: KR20137010193