DYNAMIC CLOCK DOMAIN BYPASS FOR SCAN CHAINS

• Main Authors: KUMAR PRIYESH, TEKUMALLA RAMESH C
• Format: Patent
• Language: English; Korean
• Published: 03.05.2013
• Subjects: MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

PURPOSE: A dynamic clock domain bypass for scan chains is provided to decrease test time and power consumption by detouring a part of the scan chain related with specific clock domains selectively. CONSTITUTION: An integrated circuit includes a scan test circuit and an additional circuit. The scan test circuit includes a clock domain bypass circuit. The clock domain bypass circuit is configured to detour more than one of sub chains and a scan chain having a plurality of sub chains related with each distinguished clock domain. The additional circuit is tested by using the scan test circuit. The scan chain forms a serial shift register including less sub chains than all sub chains during an operation in a scan shift mode. Other sub chains among sub chains are detoured by the clock domain bypass circuit in order not to be a part of the serial shift register at the scan shift mode. [Reference numerals] (200) Decompressor; (202) Compressor; (206-1,B1,B2,206-n_1,C1,C2,C3,C4) Cell; (207) Circuit under test; (208,210,212) Combinational logic; (AA) From a tester(102); (DD,EE) Scan chain; (FF) To the tester(102)