METHOD AND SYSTEM FOR PROVIDING MULTIPLE SELF-ALIGNED LOGIC CELLS IN A SINGLE STACK

PURPOSE: A method for providing a plurality of self-aligned logic cells in a single stack and a system thereof are provided to improve the performance of memory cells by reducing misalignment between free layers and magnetic junctions. CONSTITUTION: A memory cell stores multi-bits corresponding to a...

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Bibliographic Details
Main Authors DRISKILL SMITH ALEXANDER A.G, APALKOV DMYTRO, KROUNBI MOHAMAD TOWFIK, NIKITIN VLADIMIR
Format Patent
LanguageEnglish
Korean
Published 20.03.2013
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Summary:PURPOSE: A method for providing a plurality of self-aligned logic cells in a single stack and a system thereof are provided to improve the performance of memory cells by reducing misalignment between free layers and magnetic junctions. CONSTITUTION: A memory cell stores multi-bits corresponding to a plurality of information storage layers. Spaces and junction angles are determined in memory cells(102). A magnetoresistive stack including layers is laminated in the memory cells(104). The memory cells include information storage layers. A mask is formed on the magnetoresistive stack(106). The memory cells are defined by the magnetoresistive stack(108). [Reference numerals] (102) Determining targeted spaces and junction angles corresponding to information storage layers with different switching currents; (104) Laminating a magnetoresistive stack; (106) Providing a mask corresponding to memory cells; (108) Defining the memory cells to self-align the information storage layers
Bibliography:Application Number: KR20120100164