INSTRUCTION SET ARCHITECTURE-BASED INTER-SEQUENCER COMMUNICATIONS WITH A HETEROGENEOUS RESOURCE

PURPOSE: Communication between a different resource and an instruction set architecture(ISA) based sequencer is provided to supply a mechanism capable of communication between ISA based sequencers, thereby improving overhead and performance. CONSTITUTION: A first execution resource(50a) performs com...

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Main Authors PATEL BAIJU, HAMMARLUND PER, HANKINS RICHARD, WANG HONG, CHINYA GAUTHAM, BIGBEE BRYANT, YOSEF YUVAL, RODGERS DION, TALGAM YOAV, JIANG HONG, KAUSHIK SHIV, SHEAFFER GAD, SHEN JOHN, HELD JAMES P
Format Patent
LanguageEnglish
Korean
Published 07.03.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Summary:PURPOSE: Communication between a different resource and an instruction set architecture(ISA) based sequencer is provided to supply a mechanism capable of communication between ISA based sequencers, thereby improving overhead and performance. CONSTITUTION: A first execution resource(50a) performs commands and corresponds to a first hardware thread context. A second resource(50b) is connected to the first execution resource. The second resource includes accelerators(52a-52c) and an interface connected to the accelerators. The accelerators calculate data received from the first execution resource. The interface performs communication between resources of the first execution resource and an accelerator under user-level control. The first execution resource has first ISA. The accelerator has second ISA is comprised based on architecture state information received from the first execution resource.
Bibliography:Application Number: KR20130007136