STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE

PURPOSE: A structure and method for a single gate nonvolatile memory device are provided to improve productivity by simultaneously forming common drain and source in the same process. CONSTITUTION: A semiconductor substrate(210) includes a peripheral region(212) and a memory region(214). A gate stac...

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Main Authors TSENG HUANG WEN, TSUI YING KIT
Format Patent
LanguageEnglish
Korean
Published 28.01.2013
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Abstract PURPOSE: A structure and method for a single gate nonvolatile memory device are provided to improve productivity by simultaneously forming common drain and source in the same process. CONSTITUTION: A semiconductor substrate(210) includes a peripheral region(212) and a memory region(214). A gate stack(220) includes a first gate dielectric feature(226a) and a first gate electrode(228a). A second gate stack(222) includes a second gate dielectric feature(226b) and a second gate electrode(228b). A third gate stack(224) includes a third gate dielectric feature(226c) and a third gate electrode(228c). The second gate stack and the third gate stack are separated by an STI feature(216).
AbstractList PURPOSE: A structure and method for a single gate nonvolatile memory device are provided to improve productivity by simultaneously forming common drain and source in the same process. CONSTITUTION: A semiconductor substrate(210) includes a peripheral region(212) and a memory region(214). A gate stack(220) includes a first gate dielectric feature(226a) and a first gate electrode(228a). A second gate stack(222) includes a second gate dielectric feature(226b) and a second gate electrode(228b). A third gate stack(224) includes a third gate dielectric feature(226c) and a third gate electrode(228c). The second gate stack and the third gate stack are separated by an STI feature(216).
Author TSENG HUANG WEN
TSUI YING KIT
Author_xml – fullname: TSENG HUANG WEN
– fullname: TSUI YING KIT
BookMark eNrjYmDJy89L5WSwDw4JCnUOCQ1yVXD0c1HwdQ3x8HdRcPMPUgj29HP3cVVwdwxxVfDz99MN8_dxDPEEivi6-voHRSq4uIZ5OrvyMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JJ47yAjA0NjAwNDAxMjc0dj4lQBAD2ALNg
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID KR20130010427A
GroupedDBID EVB
ID FETCH-epo_espacenet_KR20130010427A3
IEDL.DBID EVB
IngestDate Fri Aug 23 07:04:24 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
Korean
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_KR20130010427A3
Notes Application Number: KR20120012880
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130128&DB=EPODOC&CC=KR&NR=20130010427A
ParticipantIDs epo_espacenet_KR20130010427A
PublicationCentury 2000
PublicationDate 20130128
PublicationDateYYYYMMDD 2013-01-28
PublicationDate_xml – month: 01
  year: 2013
  text: 20130128
  day: 28
PublicationDecade 2010
PublicationYear 2013
RelatedCompanies TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
RelatedCompanies_xml – name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
Score 2.8411348
Snippet PURPOSE: A structure and method for a single gate nonvolatile memory device are provided to improve productivity by simultaneously forming common drain and...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130128&DB=EPODOC&locale=&CC=KR&NR=20130010427A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3PT8IwFH5BNOpNUYOKpolmt0UYTNiBmNF2gLCNzLHgiaxsS4xmEJnx3_d1DuXEpWn6kqZt8r0f7ev3AO7DRTPWkrCuYqup6N8ipIxQVxetRITNKJFWVGZbOI-Daet5ps9K8LH5C5PzhH7n5IiIqAXiPcv19er_EovluZXrB_GGQ8sny-8ypYiOUSGjvlVYr8snLnOpQml35CmO9yuTsYfWNvdgHx3ptsQDD3ryX8pq26hYJ3AwwfnS7BRK78sKHNFN7bUKHNrFkzd2C_Stz9Cx9r0plXkKxHQYsbk_cBnBMI68DJ3-mJO-6XPioHIM3LHpD3HE5rbrvRLGgyHl53BncZ8OVFzJ_G_j85G3vezmBZTTZRpXgaCXEMdCSGp2SaaTGJEeiboQURS2jIbeuYTarpmudouv4VjLiz40VK1Tg3L2-RXfoOnNxG1-Yj-UXoEs
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bT8IwFD5BNOKbosYLahPN3hZxMIEHYkZb2GQXMgvBJ7KyLTEaIDLj3_d0gvLES9P0JE3b5DuX9vQ7AHfRtJYYaVTVsTV09G8RUq3I1Kf1VEa1OFVWVGVb-I_2sP48NscF-Fj_hcl5Qr9zckRE1BTxnuX6evF_icXy3MrlvXzDoflTV7SZtoqOUSGjvtVYp80HAQuoRmm7H2p--CtTsYfRsHZgF53shsIDH3XUv5TFplHpHsLeAOebZUdQeJ-XoUTXtdfKsO-tnryxu0Lf8hgdaxEOqcpTIJbPiMeFHTCCYRx5cfyey0nPEpz4qBxHgWsJB0c87gXhK2F85FB-ArddLqit40omfxuf9MPNZddOoTibz5IzIOglJImUippdkemkrdiMZVXKOI7qrQezeQ6VbTNdbBffQMkWnjtxHb9_CQdGXgDiQTeaFShmn1_JFZrhTF7np_cDzwyEHw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=STRUCTURE+AND+METHOD+FOR+SINGLE+GATE+NON-VOLATILE+MEMORY+DEVICE&rft.inventor=TSENG+HUANG+WEN&rft.inventor=TSUI+YING+KIT&rft.date=2013-01-28&rft.externalDBID=A&rft.externalDocID=KR20130010427A