MANUFACTURING METHOD FOR CHIP PACKAGE AND CHIP PACKAGE PRODUCED BY THE METHOD

PURPOSE: A chip package production method and a chip package which is manufactured thereby are provided to reduce costs by reducing the distance between a chip and inner lead to improve product stability. CONSTITUTION: A lead part(290) is formed in the lower side of inner lead(230) by half-etching t...

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Bibliographic Details
Main Authors PARK, CHUNG SIK, EOM, SAI RAN, LEE, HYUNG EUI, CHUN, HYUN A
Format Patent
LanguageEnglish
Korean
Published 16.01.2012
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE: A chip package production method and a chip package which is manufactured thereby are provided to reduce costs by reducing the distance between a chip and inner lead to improve product stability. CONSTITUTION: A lead part(290) is formed in the lower side of inner lead(230) by half-etching the upper side of a metallic board(200). A die-pad part(280) having a lower part connected to the lead part. The lead part and the die-pad part are formed at the same time. A chip(250) is attached to the die-pad part and the chip and the inner lead are electrically connected. A molding part(270) of insulating property which buries the chip and a connection part is formed on the metallic board. The lead part and the die-pad part are short circuited by etching the lower part of the metallic board.
Bibliography:Application Number: KR20100065776