MULTIPLE PLANE, NON-VOLATILE MEMORY WITH SYNCHRONIZED CONTROL

This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and...

Full description

Saved in:
Bibliographic Details
Main Author HAUKNESS BRENT STEVEN
Format Patent
LanguageEnglish
Korean
Published 06.12.2011
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the "program phase" and the "verify phase" of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution.
Bibliography:Application Number: KR20117021329