CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE

A block interleaver (610) for interleaving blocks of coded symbols comprises a 2-dimension word addressable DWA memory. An M-row-by-N-column array (610) of bit cells (300) is addressed by logic (242, 252) using 2-Dimension Addressing, using first and second orthogonal address spaces. The block inter...

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Bibliographic Details
Main Authors CHAIYAKUL VIRAPHOL, CHEN CHIH TUNG, KANG INYUP
Format Patent
LanguageEnglish
Korean
Published 17.09.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A block interleaver (610) for interleaving blocks of coded symbols comprises a 2-dimension word addressable DWA memory. An M-row-by-N-column array (610) of bit cells (300) is addressed by logic (242, 252) using 2-Dimension Addressing, using first and second orthogonal address spaces. The block interleaver accepts the coded symbols in blocks by filling the columns of the array, and outputs the interleaved symbols one row at a time. A corresponding de-interleaver, and ping-pong buffer (600) comprising an interleaver and de-interleaver, are disclosed.
Bibliography:Application Number: KR20107001695